The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g. transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. However, the smaller feature size may lead to more leakage current. As the demand for even smaller electronic devices has grown recently, there has grown a need for reducing leakage current of semiconductor devices.
Fin field effect transistors (FinFETs) have emerged as an effective alternative to further reduce leakage current in semiconductor devices. In a FinFET, an active region including the drain, the channel region and the source protrudes up from the surface of the semiconductor substrate upon which the FinFET is located. The active region of the FinFET, like a fin, is rectangular in shape from a cross sectional view. In addition, the gate structure of the FinFET wraps the active region around three sides like an upside-down U. As a result, the gate structure's control of the channel has become stronger. The short channel leakage effect of conventional planar transistors has been reduced. As such, when the FinFET is turned off, the gate structure can better control the channel so as to reduce leakage current.
As technologies further evolve, semiconductor process nodes have been scaled down for high density integrated circuits. As a result, the form factor of integrated circuit has been improved from shrinking the semiconductor process node (e.g., shrink the process node towards the sub-20 nm node). As semiconductor devices are scaled down, new techniques are needed to maintain the electronic components' performance from one generation to the next. For example, transistors formed by high carrier mobility materials such as group III-V materials, germanium and/or the like are desirable for high density and high speed integrated circuits.
High carrier mobility materials offer various advantages in comparison with silicon. However, silicon wafers are dominant in the semiconductor industry because of the high cost associated with high carrier mobility material wafers. One solution to fabricating high carrier mobility material based transistors is growing high carrier mobility material active regions on silicon substrates through an epitaxial growth process. When a high carrier mobility material layer is grown on a silicon substrate, the high carrier mobility material may be compressively strained to fit the lattice spacing of the silicon substrate. After the thickness of the high carrier mobility material layer surpasses a critical thickness, the strain may be relieved by forming a variety of threading dislocations. Such threading dislocations are defects, which may degrade electrical properties of high carrier mobility material based transistors. Stacking faults caused by the growth of the high carrier mobility material layer on the silicon substrate also degrade electrical properties of such transistors. Methods of reducing or eliminating threading dislocations and stacking faults may be needed.